Repeater Design to Reduce Delay and Power in Resistive Interconnect

In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current. In order to develop a repeater design methodology, a timing model characterizing a complementary metal–oxide–semiconductor (CMOS) inverter driving a resistance–capacitance (RC) load is presented. The model is based on the Sakurai short-channel -power law model of transistor operation. The inverter model is applied to the problem of repeaters to produce design expressions for determining the optimum number of uniformly sized repeaters to be inserted along a resistive interconnect line for reduced delay. For a wide variety of typical RC loads, this analytical repeater model exhibits a maximum error of 16% as compared to a dynamic circuit simulator (SPICE). The advantage of uniformly sized repeaters versus tapered-buffer repeaters is also investigated using the repeater model presented in this paper. It is shown that uniform repeaters remain advantageous over tapered buffers and taperedbuffer repeaters even with relatively small resistive RC loads. An expression for the short-circuit power dissipation of a repeater driving an RC load is presented. A comparison of the short-circuit power dissipation to the dynamic power dissipation in repeater chains and related power/delay tradeoffs are made.